A 14mW 10–bit 20–Msample/s ADC in 0.18um CMOS with 61MHz–input

We have developed a 10-bit 20-Msample/s 14mW ADC with 1.8 V single power supply. Our unique 4-stage pipelined architecture and a novel digital calibration technique has enabled us to design such a low power embeddable ADC in 0.18µm CMOS. The experimental results at 20MS/s show DNL of less than +/- 0.4 LSB, INL of less than +/-1.3LSB and SNDR of more than 52dB with 61MHz input frequency. This test chip also demonstrates direct-IF (57MHz) conversion of digital TV test system (OFDM), for which it has a good B.E.R of less than 1e-5.