Highly Efficient Stress Transfer Techniques in Dual Stress Liner CMOS Integration

Double disposable sidewall spacers (DDSW) process and adhesion reinforcement technique (ART) are proposed, for the first time, demonstrating efficient stress-transfer from the dual stress liner (DSL) to the FET channel region. A thin L-shape sidewall formed by the DDSW process was designed to compensate decreased channel stress resulted from the aggressive pitch scaling. A +10% enhancement of channel conductance has been achieved for NTETs by the DDSW process compared with a conventional DSL one. For PFETs, achieved +23% I on enhancement by using the ART, was resulted from avoiding stress degradation in the DSL process and optimizing the DSL layout.