HLS and manual design methodology for H.264/AVC deblocking filter

This paper presents two design methodologies for hardware/software (HW/SW) architectures. The first one uses High Level Synthesis (HLS) based on Catapult C Synthesis. From C++ descriptions, this design flow is able to automatically produce hardware blocks that can fully operate with CPU cores on Xilinx prototyping platforms (FPGA). The second methodology relies on a manual RTL (Register Transfer Level) design to produce potentially better optimized IPs. To evaluate the performance of each flow, an application/design study using both methodologies is made on an optimized deblocking filter function, which is part of a complete H.264/AVC video coding system. A tradeoff between design time and performance is presented and discussed with respect to both methodologies: The HLS design flow time is less than the half of manual design flow time. However, the application throughput, in term of kilosMacroblock per second, is more than three times speeder when using a manual design.