Measurement and Analysis of Statistical IC Operation Errors in a Memory Module Due to System-Level ESD Noise

Voltage noise and operation errors in an integrated circuit (IC) due to electrostatic discharge (ESD) events were measured, validated, and analyzed in this paper. A simplified structure of a laptop personal computer and an IC with a D-type flip-flop were designed and manufactured for the experimental tests. Every signal input to the IC was simultaneously measured during the ESD tests, and validated with the simulated results using a full-wave solver and a simple circuit model. Next, SPICE simulations were conducted using the measured voltages with ESD tests. The output waveforms and the statistical occurrence ratios of the operation failures found from the SPICE simulations were compared with measured values. Furthermore, the effects of decoupling capacitors on the IC operation failures due to ESD were investigated.