Conditions for Internal Transport Barrier Formation in JET

A circuit for performing operations on two bits (A,B), including the processing of a carry from a preceding circuit ( &upbar& C) and transmitting it to a subsequent circuit ( &upbar& C). The circuit includes a network which is formed by MOS transistors which can be programmed via programming lines and which supplies a logic combination. An exclusive carry-propagation-generation device is formed by three MOS transistors which are connected in series between a carry-propagation line and ground and whose gates are connected to one of the bits to be processed, to the logic combination, and to a carry inhibit line, respectively.