Readout channel with majority logic timestamp and digital peak detector for Muon Chambers of the CBM experiment

A prototype readout channel was manufactured in UMC CMOS 180 nm for the purpose of the CBM experiment at the FAIR accelerator. The channel includes a preamplifier with fast and slow CR-RC shapers, discriminator with a differential threshold setup circuit, a 6-bit SAR ADC (DNL = 0.70, INL = 0.45), digital peak detector and block of the time stamp registration. The control data, clock and output data are supplied through SLVS transmitter and receiver. The slow and fast channels have 1000 el and 1500 el ENC accordingly at a 50 pF detector capacitance. Power consumption is 10 mW/channel.