A 283-GHz Fully Integrated Phase-Locked Loop Based on 65-nm CMOS

A 283-GHz fully integrated phase-locked loop (PLL) based on a 65-nm CMOS technology is presented. A triple-push ring voltage-controlled oscillator and a frequency divider chain (/16,384) composed of 2 injection-locked frequency dividers are developed, which are integrated with 12 current-mode logic frequency dividers, a phase frequency detector, a charge pump, and a loop filter. The fabricated PLL showed a locking range of 282.3–283.7 GHz and a phase noise of −53.5 dBc/Hz at 100 kHz (in band) and −78.6 dBc/Hz at 10 MHz (out of band). Total dc power consumption is 114 mW. The chip occupies 920 × 520 μ m 2 excluding probing pads.