Old Web
English
Sign In
Acemap
>
Paper
>
Analysis of pattern area reduction for logic circuit and system LSI with SGT
Analysis of pattern area reduction for logic circuit and system LSI with SGT
2015
Tomohiro Yokota
Shigeyoshi Watanabe
Keywords:
% area reduction
Computer hardware
Logic gate
Computer science
Correction
Source
Cite
Save
Machine Reading By IdeaReader
9
References
0
Citations
NaN
KQI
[]