Modified Selective Harmonics Mitigation PWM for a Switched Diode Multilevel Inverter

A modified selective harmonic mitigation (SHM) technique for multilevel inverters considering the RMS output voltage magnitude is presented. The harmonic contents in the output voltage of these inverters must satisfy the specified grid code requirement standards. In conventional SHM techniques, the firing angles of the multilevel inverters have been derived by taking into account grid code harmonic reduction standards. When the multi-level inverters are driven with these firing pulses generated, it results in reduction of the magnitude of the inverter output voltage. In order to overcome this issue of output voltage reduction, the modified SHM optimization problem includes another constraint on the RMS output voltage limits, which results in different set of firing angles. This facilitates the use of firing angles, which takes into account the grid code standards of harmonic mitigation without compromising the value of the RMS output voltage of the inverters. The proposal has been simulated and validated in MATLAB Simulink and the experimental results are obtained for a single-phase seven level inverter with Silicon made semiconductor switches. By using the proposed method, output voltage THD (upto 40th harmonics were considered) of 5.9 % was obtained, which is well below the harmonic standards specified by EN 50160.