FPGA Implementation of Random Vector Functional Link Networks based on Elementary Cellular Automata

Today, there is an increasing demand in designing and deploying low-power Machine Learning (ML) models for edge applications such as mobile phones or specific purpose smart cameras and voice processing systems. These products might incorporate low power processors and ASICs to manage communications and meet power/energy consumption specifications in computationally intensive tasks. These ML tasks usually include Deep Learning systems that require a considerably number of multiply-accumulate (MAC) operations, thus impacting in both hardware and energy requirements. Here we show a novel ML hardware design optimized for edge applications that considerably reduces the number of MAC operations based on incorporating Elementary Cellular Automata within a Random Vector Functional Link Network architecture. As a proof of concept, the proposed system is implemented in a Field-Programmable Gate Array and applied to the well known MNIST dataset, showing high-performance characteristics along with a considerably higher energy efficiency if compared with recently published ML-hardware designs.