Modeling of Fermi-Level Pinning Alleviation With MIS Contacts: n and pMOSFETs Cointegration Considerations—Part II

In this paper, the insertions of dielectric in metal/insulator/semiconductor contacts are considered via their associated impact on the dc and ac performances. Based on dc output characteristics projections, we found that single insertion and/or single-metal integration schemes are unlikely to result in simultaneously successful Fermi-level pinning alleviation on both n and pFETs. We show that the added $C_{\mathrm { {MIS}}}$ contributes to a significant extra improvement in terms of intrinsic inverter delay. In particular, an optimal configuration consisting of Pt-liner/ p-Si and Zr/TiO 2 (15A)/n-Si contacts can lead to a ring oscillator frequency higher than that of p and nFETs each flanked by ideal ohmic contacts with $10^{-9}~\Omega \cdot {\mathrm{ cm}}^{2}$ resistivity.