Clock locking method and device of multi-phase clock generating system

The invention provides a clock locking method and device of a multi-phase clock generating system. The system comprises a digital delaying chain formed by N DCDLs. Each DCDL comprises a first DC chain and a second DC chain. Each first DC chain comprises at least one first DC. The method comprises the steps that delaying of each first DC chain is adjusted according to adjusting codes, and when a clock phase output by the digital delaying chain lags behind a reference clock phase, first-time locking is carried out; the last single bit of the adjusting codes during locking is reset, so that delaying of the digital delaying chain backspaces by delaying of the N first DCs, and then first clock signals are output; according to the first clock signals and the reference clock signals, remainder codes are generated; and according to the remainder codes, the phase difference between the first clock signals and the reference clock signals is evenly compensated into the digital delaying chain with delaying of the second DCs as units, and accordingly the delaying errors between the phase of the first clock signals output by the multi-phase clock generating system and the phase of a reference clock are reduced.