Performance analysis of multi-dimensional packet classification on programmable network processors

Multi-field packet classification is frequently performed by network devices such as edge routers and firewalls - such devices can utilize programmable network processors to perform this computation-intensive task at nearly line speeds. The architectures of programmable network processors are typically highly parallel and a single algorithm can be mapped in different ways onto the hardware. We study the performance of two different design mappings of the bit vector packet classification algorithm on the Intel/sup /spl reg// IXP1200 network processor. We show that: (i) overall, parallel mapping has a better packet processing rate (25% more) than pipelined mapping; (ii) in parallel mapping, a processing element's utilization can be considerably affected by code complexity, in terms of branching, because of significant time wasted (as much as 40% more) due to aborting instruction execution pipelines; (iii) in pipelined mapping, multiple memory reads per packet can lower the overall performance.