High Hole Mobilities in Fully-Strained Si Ge Layers and their Significance for SiGe pMOSFET Performance

cm . The measured room temperature mobilities are consistently higher than the equivalent Si inversion layer mobilities and these results have been incorporated into two-dimensional (2-D) device simulations in order to understand their significance for SiGe pMOS device performance. It is found that improvements in current drive can be obtained, but only for the most aggressive vertical architectures. For Si cap thickness greater than 1.5 nm, parallel conduction in the cap layer counteracts much of the advantage of the high mobility channel and, even for thin Si caps, velocity saturation effects at high lateral electric fields significantly limit the current drive of a SiGe pMOSFET to values close to that of the conventional Si device. The diminished gate control, due to the inclusion of the cap layer, and the smaller SiGe bandgap also lead to a significant deterioration of the subthreshold characteristics.