High spatial resolution monolithic pixel detector in SOI technology

Abstract This paper presents test-beam results of monolithic pixel detector prototypes fabricated in 200 nm Silicon-On-Insulator (SOI) CMOS technology studied in the context of high spatial resolution performance. The tested detectors were fabricated on a 500 μ m thick high-resistivity Floating Zone type n (FZ-n) wafer and on a 300 μ m Double SOI Czochralski type p (DSOI Cz-p) wafer. The pixel size is 30 μ m  ×  30 μ m and two different front-end electronics architectures were tested, a source follower and a charge-sensitive preamplifier. The test-beam data analyses were focused mainly on determination of the spatial resolution and the hit detection efficiency. In this work different cluster formation and position reconstruction methods are studied. In particular, a generalization of the standard η -correction adapted for arbitrary cluster sizes, is introduced. The obtained results give in the best case a spatial resolution of about 1.5 μ m for the FZ-n wafer and about 3.0 μ m for the DSOI Cz-p wafer, both detectors showing detection efficiency above 99.5%.