3D integration technology for set-top box application

In this paper, the technological bricks specifically developed for 3D integration of a set top box demonstrator will be presented. The integration flow was based on the 45 nm technology top chip stacked on a 130 nm technology active bottom wafer [1]. This flow needed to develop specific wafer level packaging technologies such as: • Top chip & bottom chip interconnections • High aspect ratio TSV included into the bottom wafer • Backside interconnections for subsequent packaging step • Temporary bonding and debonding of bottom wafer • Top chip stacking on bottom wafer The complete process flow will be presented. Then, a technical focus will be done on the backside interconnections step. Finally, the electrical results achieved on a specific test vehicle, similar to the demonstrator will be discussed.