Low Power Fir Filter Design Using Truncated Multiplier

In this paper Low-cost finite impulse response(FIR) design are presented using the concept of faithfully rounded truncated multipliers. We jointly consider the effective of bit width and hardware resources without sacrificing the frequency response and output signal accuracy. Non-uniform coefficient quantization with proper filter order to minimize the cost of total area. Multiple constant multiplication/accumulation in a pipelined direct FIR structure is implemented using an improved version of truncated multipliers. Comparisons with previous FIR filter design approaches show that the proposed design achieve the best area and power results. Index Terms—Digital signal processing (DSP), faithful rounding, truncated multipliers, FIR filter design.