D-Pack 3D Interposer Decoupling System

D-Pack three-dimensional interposer decoupling system presents a new and fundamentally improved design for high-speed microprocessor decoupling schemes. D-Pack is intended for the decoupling needs of today’s most advanced microprocessors. The base element of the D-Pack is a low inductance, multi-terminal, multilayer capacitor (MLCC) or D-Stick TM . D-Sticks may be combined in numerous configurations to form D-Packs suitable for myriad microprocessor designs. In addition to the decoupling function, D-Pack also provides for power and ground feed circuits between the microprocessor package and the parent circuit board. D-Pack is advantageous in that it eliminates appendage circuitry and the associated parasitic inductance, typical of topside decoupling schemes, while enabling a reduced package footprint combined with enhanced thermal management relative to bottom side decoupling schemes. Each D-Stick TM within a D-Pack also serves as an effective feed through filter capacitor as well as providing an excellent thermal conduction path between the microprocessor package and the parent circuit board. D-Pack offers a unique combination of high capacitance density, low inductance, low ESR, nearly perfect noise filtering, and enhanced thermal management in a space saving design. Capacitance densities are available in excess of 1,000 µF/in 2 (>150 µF/cm 2 ). Equivalent series inductance (ESL) values of 1 pH or less, combined with power noise filtering with a maximum insertion loss (IL) of nearly 120 dB are possible. D-Pack designs may enable a significant reduction (<25% or more) in package foot print as well as enhanced thermal performance.