Device Mismatching and Random Telegraph Signal In Digital Pixel Imagers On 90-nm CMOS Process

The interest and need for more digital processing and functionality in the readout circuits continue to grow rapidly while the pixel pitch is getting smaller and this trend continues from visible to long wave IR. For a fully digital design (i.e. A/D in the pixel), the digital circuit can consume a large portion of the available space depending on the process feature size, effective well capacity (absolute dynamic range), and in-pixel functionality. The upside is that the digital circuit scales with the process node. The down side is limiting available space for the analog (front end) portion of the pixel limiting the designs to CMOS processes with smaller feature size. As we previously reported on 55- and 65-nm designs, this paper shows results from two imagers fabricated on the 90-nm process. In addition to Random Telegraph Signal/Noise (RTS/N), this paper compares non-uniformity between the two designs with device mismatching being the main culprit.