Direct Monitoring of EOT‐JLEAK Characteristics for SiON and High‐k Gate Dielectrics

A new FEOL metrology technique based on the use of elastic material probes (EM‐Probes) is demonstrated for gate dielectric process development and monitoring for the 45 nm technology node and beyond. It is shown that critical gate dielectric electrical parameters such as Equivalent Oxide Thickness (EOT), Gate Leakage Current Density (JLEAK), and Stress Induced Leakage Current (SILC) can be accurately measured in a non‐damaging, non‐contaminating fashion on product wafers. Correlations to final device parameters are discussed which are better than any other method available.