9.5×9.5mm 2 -Area Recrystallization, 6μm-Viahole Filling and Thin 1/4μm CMOS SOI Designing for Realizing Three-Dimensional Integrated Circuit
1991
Several key technologies;large-area recryatallization technique, viahole-filling, and scaled thin SOI devices, have been prepared for realizing 3D LSI.
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