The combined fins having recesses for coupling the liner to enhance stress soi fin fet

FET fin having a fin FET and a method of stress liner recess for manufacturing. A method comprising providing an SOI substrate having a fin, forming a gate on the fin, forming offset spacers on the gate, the epitaxially grown film to incorporate fins, around the gate the dummy spacer is deposited, and the epitaxial film such that the combined recess. Silicide is then formed in the recess merge epitaxial film stress liner after deposition on the fin FET. By using an epitaxial process combined recess may be formed (i.e., perpendicular to the substrate) perpendicular to the MOSFET having a silicide. The vertical extension improved resistance silicide.