Hybrid DAC capacitor array structure

The invention discloses a hybrid DAC capacitor array structure which comprises n C2C capacitor array units, m binary capacitor array units and a redundant capacitor. A node corresponding to the first bit in the n C2C capacitor array units is connected with the redundant capacitor and serves as the input end of the capacitor array structure, a node corresponding to the nth bit is connected with nodes corresponding to the bits from the n+1th bit to the n+mth bit to serve as the output end of the capacitor array structure, and a lower electrode plate of the capacitor at the lower end of each node is connected with a selection switch. The C2C capacitor array units and the binary capacitor array units are combined, so that the structure has the advantages that precision of a binary weight capacitor array structure is high and power consumption of an attenuation capacitor array structure is low, and the requirements for low power consumption and high precision of various simulation electronic devices can be better met by controlling the composition ratio of the C2C capacitor array units and the binary capacitor array units.