A New Analytical Model for Gated Turn-off of

In this paper, a new two-dimensional analytical model is developed to physically explain the storage phase of the turn-off mechanism in a gate turn-off thyristor. An expres- sion is obtained from first principles for the position of the "on" region plasma edge as a function of time, assuming a negative ramp for the gate current. The model contains no fitting pa- rameters and addresses realistic issues such as high-injection effects, variation in the base transport factors, and the physical basis for the minimum "on" region dimension that are not treated in any previous analysis. At the end of the storage time, the active injecting area of the cathode emitter reaches some minimum value which is cal- culated by imposing the condition that the supply of holes into the plasma region at that point of time is no longer sufficient for sustaining a flow of electrons across the p base. Our model, for the first time, investigates analytically, the nature of vari- ation of the storage time with anode current, rate of gate cur- rent ramp, and cathode island width. Experimental data from our storage time measurements on General Electric, Malvern, PA, devices are in excellent agreement with analytically pre- dicted values of storage time versus anode and gate currents, and substantiate, for the first time, previous experimental ob- servations for their dependence on cathode island width.