Technology Limits and compact model for SiGe Scaled FETs

Stress relaxation in strained-Si MOSFETs can be significant in the presence of compressive stress imposed by trench isolation, especially for highly scaled active regions. Stress of the strained region is reduced by ∼2/3 when the active region is scaled from Lactive=0.4 µ mt o 0.1µm. Mobility can be lower by 50 % for narrow active widths resulting from the strain relaxation. The strain relaxation may restrict the use of strained-Si MOSFETs for technology nodes beyond 25 nm. Electrical and thermal characteristics of strained-Si devices are investigated and a compact junction capacitance model for strained-Si MOSFET suitable for circuit simulation is proposed.