Recent advances in low-power CMOS-coherent digital-signal-processing (DSP) technologies (Conference Presentation)

This invited talk reviews recent technology advances in our three generations of low-power CMOS coherent digital signal processor (DSP) implemented with 40, 20, and 16-nm CMOS technologies, with highlights on its functional integration, adaptation, and design optimization for power-efficiency CMOS DSP implementation. The latest 16-nm third-generation (Gen3) DSP implementation achieves sub-10-watt per 100 Gb/s coherent transmission in both 100G DP-QPSK and 200G DP-16QAM transport modes for the first time, and experimentally confirms its trade-off between transmission performance and power dissipations.