A 40-nm 16-Mb Contact-Programming Mask ROM Using Dual Trench Isolation Diode Bitcell

A 16-Mb mask read-only memory (ROM) chip based on a novel diode structure is proposed. The diodes are constructed by buried n-type implantation layer and heavily doped p-type diffusion layer. With dual-trench isolation process and borderless contact scheme, the diode array can realize ultrahigh density. The fabricated mask ROM chip using 40-nm CMOS bulk technology is wired with three levels of metal, only two levels for diode arrays. The effective diode size is as small as 0.017 $\mu \text{m}^{\mathrm { {2}}}$ , which is the smallest bitcell of commercial mask ROM products in the world, to our best knowledge. The physical array density can achieve approximately 0.0225 mm $^{\mathrm { {2}}}$ /Mb. Test results indicate that chip standby leakage current is $ at 25 °C and $ at 85 °C with 2.5 V supply voltage. Array standby leakage is $ /Mb at 25 °C and $ /Mb at 85 °C with 2.5 V supply voltage.