Analysis and Comparison of Methods to Reduce Leakage Power and Latency to Improve Performance of VLSI Circuits

Power dissipation in one of the major concerns of VLSI circuit designers with the launch of battery held devices and applications, power consumption in the circuit also increased exponentially. Leakage current became an overriding factor in nanometer CMOS design technologies. This paper provides a comprehensive study, analysis and comparison of leakage power reduction technique such as zigzag approach, multi threshold approach, sleepy stack, dual sleep, transistor gating etc.. All the above methods are tested and analyzed using microwind EDA tool.