BTI reliability of InGaAs nMOS gate-stack: On the impact of shallow and deep defect bands on the operating voltage range of III-V technology

In this work, we show that the reliability of InGaAs channel MOS devices not only depends on density of shallow defect states (i.e., electron traps responsible for PBTI in Si devices), but it is also governed by the density of deep defect states. This limits the operating range of the device. We conclude that it is necessary to characterize both shallow and deep defect densities in order to determine the total operating window (i.e., maximum underdrive and overdrive) of III-V devices for future technologies. We also show that a gate-stack comprising of a new ASM interface layer (ASM-IL), a LaSiO x interlayer and high-k dielectric can achieve the required reliability targets for a low power technology such as III-V.