Improvement of ramp fabrication for high-Tc ramp-edge Josephson junction

The fabrication process of ramps for HTS ramp-edge Josephson junctions was studied. We refined a photolithography method for producing ramps having smooth surfaces without a tail structure and similar angles in a chip. Optimization of resist reflowing parameters was crucially important. It was found that excessive reflowing gave rise to an increased spread in the angles. We demonstrated fabrication of smooth ramps with a small spread in their angles using a mask pattern for a toggle flip-flop circuit pattern by using the optimized reflowing parameters.