Transverse nanowire interdigital-structure transistor based on SOI substrate and preparation method

Provided is a transverse nanowire interdigital-structure transistor based on a SOI substrate. The transverse nanowire interdigital-structure transistor comprises the SOI substrate, a source region, a drain region, multiple silicon nanowires, multiple III-V group nanowires, a SiO2 buffer layer, an insulated dielectric layer, a source electrode, a drain electrode, and a gate electrode. The multiple silicon nanowires are arranged on the top silicon on the SOI substrate and are connected with the source region and the drain region alternately to form an interdigital structure. The multiple III-V group nanowires are bridged on the sidewall silicon crystal surfaces of the multiple silicon nanowires. The SiO2 buffer layer is produced on the surfaces of the source region, the drain region, and the multiple silicon nanowires. The insulated dielectric layer is produced on the surfaces of the multiple III-V group nanowires and the SiO2 buffer layer and completely wraps the multiple III-V group nanowires. The source electrode is produced over the source region. The drain electrode is produced over the drain region. The gate electrode is produced on the multiple silicon nanowires and the multiple III-V group nanowires and wraps the multiple silicon nanowires and the multiple III-V group nanowires. The nucleation rate of the III-V group nanowires is improved.