The analysis of optical lithography at 2-dimensional dense structure

New concepts about transistor structure are being introduced for sub-50nm memory products. As the memory cell design is shrinking down, conventional transistor of planar structure can not guarantee safe transistor operation. Newly introduced transistor has to ensure robust transistor operation characteristics and process stability simultaneously. One of the candidates which are being developed recently is vertical transistor. The basic layout to integrate vertical transistor include very dense 2-dimensional features. The new memory cell based on dense structure can also contribute to reduction of cell area compared to conventional memory cell such as 8F2 planar cell. While new memory structure enables the reduction of chip size, its 2-dimensional structure limits resolving performance of optical lithography inevitably. It is very challenging to build 4F2 dense features of sub-50nm node by single exposure technology using hyper NA ArF lithography before the EUV era. In this paper, the feasibility of 2-dimensional dense structure at 50nm node is presented and various techniques are introduced to realize new memory scheme as next generation memory cell structure.