Direct Resist Removal Process from Copper-Exposed Vias for Low-Parasitic-Capacitance Interconnects

A resist stripping process from Cu-exposed vias is developed to reduce the thickness of high permittivity (high-k) SiN in Cu/low-k interconnects. A low power, low temperature O 2 reactive ion etch is proposed to suppress the significant Cu oxidation. Additionally, removing Si contents from the Cu surface is found to be critical, This resist stripping process is successfully applied to the fabrication of Cu/low-k interconnect test devices using silicon oxycarbide (k = 3.3). Low resistance, 0.25 μm diam via connections were achieved. Time dependent dielectric breakdown lifetime tests showed that even 25 nm thick SiN has a sufficient barrier property against Cu diffusion, showing that the SiN thickness reduction is also feasible from the reliability viewpoint. By thinning SiN to less than 25 nm, over 5-10% reduction in k can be achieved even when using the same low-k interlevel dielectric.