System Data Flow Pipelining for Embedded Heterogenous SoCs using OpenVX

Due to end of Dennard Scaling, the latest chip architectures are multi-core, with each core customized for specific domains e.g. computer vision, deep learning, graphics, signal processing, image processing etc. However, software has not evolved to utilize such heterogeneous (or asymmetrical) multi-core architectures to improve performance and latency. The key challenge of multi-core programming is efficient implementation within the context of an easy to use open software framework with high utilization. This paper presents an efficient software architecture to parallelize the execution of multiple processing cores using standard Khronos OpenVX framework. The paper proposes multiple novelties, namely, extension to the standard Khronos OpenVX, multi-CPU buffer exchange, non-blocking processing stall, early buffer release and late buffer submit. The proposed implementation is done on TI Jacinto 7 platform enabling multi-core utilization of 99% (less than 1% overhead) maintaining real time performance for surround view analytics application for automotive market.