A 15-bit 30 MS/s 145 mW three-step ADC for imaging applications

A 15-bit 30 MS/s three-step ADC for imaging applications is presented with a peak-to-peak signal to rms noise ratio of 84 dB. The offsets of the residue amplifiers are independently background calibrated. The ADC is realized in single poly, 0.18 /spl mu/m CMOS, measures 1.4 mm/sup 2/ and dissipates 145 mW from 1.8 V and 3.3 V supplies.