A 200 MHz RISC microprocessor with 128 kB on-chip caches

The 32b PA-RISC 1.1 microprocessor features 64kB, two-way set-associative instruction and data caches on-chip, a controller for off-chip second-level cache of 256kB to 64MB, and an on-chip main memory and I/O controller. It operates up to 200MHz, with performance of 7.75 SPECint95 and 7.56 SPECfp95 in a 16OMHz system. The processor core is leveraged from a previous design, with circuit, fabrication process, and microarchitecture enhancements for improved performance and reduced power consumption. Circuit design allows high-frequency operation in the 0.5/spl mu/m, 3.3V CMOS process.