Increasing SoC Dependability via Known Good Tile NoC Testing

Advanced CMOS technology possibilities, power, communication and flexibility issues as well as the design gap are directing System-on-Chip (SoC) platforms towards Network-on-Chip (NoC) interconnected identical processing tiles (PT) such as the Montium processor [1]. It is broadly acknowledged that advanced technologies below 45nm come with significant yield and reliability problems, necessitating dependable designs [2]. Our approach for a dependable SoC heavily depends on the regularity within our streaming-data applications SoC. The chip consists of many identical NoC segments and identical PT’s. Boundary condition is that target applications do not require all available fault-free resources, such as routing segments and PTs.