A Hardware Implementation of SHA3 Hash Processor using Cortex-M0

This paper describes a SHA3 hash processor that is interfaced with Cortex-M0 to be used as an IP. The SHA3 hash processor was designed with a round-iterative structure of 1600-bit data-path, and it supports four different message digest sizes of 512, 384, 256, and 224 bits depending on the hash function used. The SHA3 processor interfaced with Cortex-M0 was verified by FPGA implementation. It was estimated to have a throughput of 5 Gbps at the maximum clock frequency of 289 MHz, and it occupied 1,692 slices of Virtex5 FPGA device.