RF Characterization of Vertical Wrap-Gated InAs/High- $\kappa $ Nanowire Capacitors

This paper presents RF as well as low-frequency capacitance–voltage ( $C$ – $V$ ) characterization of vertical wrap-gated InAs/high- $\kappa $ nanowire MOS capacitors. A full equivalent circuit model for traps is used to fit the low-frequency $C$ – $V$ characteristics, from which the interface trap density ( $D_{\mathrm {it}}$ ) and border trap density ( $N_{\mathrm {bt}}$ ) are evaluated separately. The results show comparable $N_{\mathrm {bt}}$ but far lower $D_{\mathrm {it}}$ ( $ eV $^{-1}$ cm $^{-2}$ near the conduction band edge) for a nanowire MOS gate-stack compared with planar references. In the RF domain, the influence of nanowire series resistances become significant, and by introducing a distributed $RC$ -model, the nanowire resistivity ( $\rho _{\mathrm {nw}}$ ) is evaluated from the capacitance data as a function of the gate bias. An ON/OFF $\rho _{\mathrm {nw}}$ ratio of $10^{-2}$ is obtained for the best device. Using the measured data, the quality factor is finally evaluated both for fabricated and ideal capacitors. The results agree well with simulated data.