다중 채널의 스큐 최소화를 위한 직렬 변환기 회로 구현 및 분석

This paper presents a two pairs 20 to 1 serializer(SER) for multi channel high speed serial interface transmitter. Two transmitted serial data which has small skew can make a size and power of receiver smaller by sharing Clock and Data Recovery(CDR). To minimize burden of receiver, two adjacent channel output skew is reduced by sharing a clock divider and a symmetrically balanced layout. Designed in a 28nm CMOS technology, the SER operates from 800Mbps-3200Mbps while consuming 1.84mW at 3200Mbps.