On the vertical leakage of GaN-on-Si lateral transistors and the effect of emission and trap-to-trap-tunneling through the AIN/Si barrier

Vertical leakage in lateral GaN devices has a significant contribution to the overall off-state current at high blocking voltages and high temperatures. It could could lead to premature breakdown before avalanche or dielectric breakdown occur. This paper identifies via experimental results and TCAD simulations the main physical mechanisms responsible for the vertical leakage through the epi and transition layer structure: (i) silicon impact ionization, (ii) electron injection across the AIN nucleation layer/silicon interface, (ill) space charge limited current. In particular, the trap-to-trap model, accounting for the leakage current across the nucleation layer, was implemented showing to be dominant at lower voltages (<200V).