Optimization of pipelined ADC architecture for Monolithic Active Pixel Sensors

For CMOS monolithic active pixels sensor readout, we developed two architectures of low power and low signal pipelined analog to digital converter (ADC) which are 5 bit, 25 MS/s pipelined ADC and 4 bit, 50 MS/s double sampling ADC. Both architectures include a non-resetting sample and hold stage to amplify the signal by a factor of 4. Due to the very low level of the incoming signal, this first stage compensates both of the amplifier offset effect and the input common mode voltage dispersion. The traditional pipelined ADC consists of three 1.5 bit sub-ADC and a 2 bit flash. And the double sampling architecture consists of one double channel 2.5 bit stage followed by a 2 bit flash stage. We present the results of prototypes, made of eight ADC channels. A comparative study is done. For the above designs, the full analog part of the converter can be quickly switched to a standby idle mode in less than lus; thus reducing the power dissipation to a ratio better than 1/1000. This fast shutdown is very important for the ILC vertex detector as the total DC power dissipation becomes directly proportional to the low beam duty cycle.