An ultra low-power rail-to-rail comparator for ADC designs

This paper presents a novel ultra low-power rail-to-rail comparator which can be suitably used in low-to-medium speed A/D converters. This comparator adopts a preamplifier followed by a dynamic latch structure to achieve fast-decision, high-resolution as well as reduced kick-back noise. A new adaptive power control technique is used to reduce the power consumption of the preamplifier. The circuit is designed and simulated in Global Foundries 65nm CMOS technology. The simulation results have shown that the power consumption of 12-bit comparator is 191.2 nW at the clock frequency of 15 MHz and 0.8 V supply voltage with a delay of 1.17nS.