Programmable array clock/reset

PROBLEM TO BE SOLVED: To minimize skew between clock signal and reset signals applied to logic cells and expand distribution choices by using a low-skew signal distribution architecture to distribute the clock and reset of a programmable array. SOLUTION: The programmable logic array(PLA) consists of sectors in, for example, a 7×7 matrix array and each sector is equipped with logic cells 22 in, for example, an 8×8 matrix array. Signal supply from the column clock line and reset line 124 and 126 to a cell 22 selected by an input multiplexer 128 and a cell combination logic circuit 120 responding to a program in a memory M1 is controlled by a programmable multiplexer 130 and the output of the cell 22 is also controlled by a programmable multiplexer 132. Therefore, when the size of signal source buffering, multiplexer buffering, etc., is determined according to a signal transmission distance, a programmable array clock/ reset signal distribution network which minimizes signal skew is obtained.