Master of Electrical Engineering Program

a full system around the MEMS RF GPS front-end designed by students in the Bhave research group. The BRC group has designed a 16-bit architecture targeted for power constrained embedded applications. The architecture is implemented with a three stage pipeline capable of running at approximately 50 MHz and 35 mW of power, in under an area of 4mm 2 , and with no DRC, IR, or hold time issues. In addition, the design includes several special instructions to optimize the eciency of GPS signal acquisition and tracking. The group has produced a full layout for the design which is currently in queue to be fabricated using the IBM 0.13um 8RF process. The design will eventually allow for the integration of a full GPS system-on-a-chip, using the custom software algorithms to enable GPS tracking. The BRC group also completed a full port of the GCC compiler, including the assembler, linker, and all necessary libraries. The team also developed several other custom scripts to test verification, including a random case generator, a software simulator for our architecture, and an automated Verilog testing and coverage tracking system.