Sampled time domain analysis of digital pulse width modulation for feedback controlled converters

Digital pulse width modulation (DPWM) is the main process involved in power conversion of digitally controlled switching power converters. Sampling frequency of analogue to digital (A/D) converter and clock frequency of digital controllers are the two constraints which create time delay in output of the modulator gating pulses. Time delay produces the major effect in terms of low frequency oscillations when the converter operates at high switching frequency. In this study the effect of sampling frequency and clock frequency has been analysed in time domain. The aim of this study is to develop instantaneous mathematical equations for DPWM output, rising edges delay, falling edges delay and develop the analytical method through which the effect of sampling frequency and clock frequency can be minimised. The uniform multisampling technique has been used to develop the mathematical equations for different types of carriers. The clock frequency has been considered for higher frequency operation of the converters. The modulator delay depends upon the sampling frequency, clock frequency, modulation index of modulating to control signal, and the rate of change of the modulating signal. The analytical results are verified through the Xilinx system generator MATLAB/Simulink simulation, and the laboratory experimental results.