A DMA and CACHE-based stress schema for burn-in of automotive microcontroller

Thermal and electrical stress phases are commonly applied to automotive devices at the end of manufacturing test to give rise to early life latent failures. This paper proposes a new methodology to optimize the stress procedures during the Burn-In phase. In the proposed method, stress of CPU, RAM memory and FLASH memory are run in parallel using DMA and CACHE interventions. The paper reports also some experimental results gathered in an automotive microcontroller, and a comparison between traditional and parallelized burn-in stress technique is also provided.