Analyzing the impact of the Operating System on the Reliability of a RISC-V FPGA Implementation

Front-end designs of OS-powered SoCs are developed to be implemented on SRAM-based FPGAs, which can be used in low-cost space applications. In this work, we evaluate the impact of OS on the reliability of a RISC-V based SoC, against configuration memory upsets. The results show that these upsets in the presence of OS barely affect the number of silent data corruptions, whereas the single event functional interruption rate increases about 3.6 times as compared to the bare-metal program execution. We also conclude that single event functional interruption rate due to configuration memory upsets show less dependence on the user application workload as compared to silent data corruption rates.