PAPER Special Section on VLSI Design and CAD Algorithms Way-Scaling to Reduce Power of Cache with Delay Variation

SUMMARY The share of leakage in cache power consumption in-creases with technology scaling. Choosing a higher threshold voltage ( V th )and/or gate-oxide thickness ( T ox ) for cache transistors improves leakage,but impacts cell delay. We show that due to uncorrelated random within-die delay variation, only some (not all) of cells actually violate the cachedelay after the above change. We propose to add a spare cache way to re-place delay-violating cache-lines separately in each cache-set. By SPICEand gate-level simulations in a commercial 90nm process, we show thatchoosing higher V th , T ox and adding one spare way to a 4-way 16KB cachereduces leakage power by 42%, which depending on the share of leakagein total cache power, gives up to 22.59% and 41.37% reduction of total en-ergy respectively in L1 instruction- and L2 unified-cache with a negligibledelay penalty, but without sacrificing cache capacity or timing-yield. key words: leakage, power reduction, cache, within-die variation, delayvariation, way scaling