A 13-mW 64-dB SNDR 280-MS/s Pipelined ADC Using Linearized Integrating Amplifiers

A 12-bit pipelined analog-to-digital converter (ADC) using a new integration-based open-loop residue amplifier topology is presented. The amplifier distortion is cancelled with the help of an analog linearization technique based on a tunable input-driven active degeneration. Amplifier gain and nonlinearity errors are detected in background using split-ADC calibration technique. The mismatch between the two half-ADCs is minimized by sharing the residue amplifier between the two half-ADCs and adding the calibration offset over time. Based on this “split-over-time” calibration architecture, a two-lane prototype ADC was fabricated in 28-nm CMOS that achieves 64-dB signal-to-noise + distortion ratio and 77dB spurious-free dynamic range at Nyquist input after calibration. Operating at 280 MS/s, the ADC consumes 13 mW from 1-V supply, exhibiting a Schreier figure-of-merit of 164.3 dB. By dissipating only 0.4 mW in the residue amplifiers, the linearization technique helps the ADC achieve an improvement of at least 3 dB in Schreier FoM over existing state-of-the-art ADCs with comparable architectures.